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1 www.semtech.com sc2596 low voltage integrated ddr termination regulator power management septenber 24, 2009 typical application circuit the sc2596 is an integrated linear ddr termination device, which provides a complete solution for ddr termination regulator designs; while meeting the jedec requirements of sstl-2 and sstl-18 specifications for ddr-sdram termination. the sc2596 regulates up to +/- 2.5a for ddr-i and +/- 1.5a for ddr-ii application requirements. v tt is regulated to track the v ref voltage over the entire current range with shoot through protection. a v sense pin is incorporated to provide excellent load regulation, along with a buffered reference voltage for internal use. the sc2596 also features a disable function which is to tri-state the output during suspend to ram (str) states by pulling the en pin low. ? ddr-i and ddr-ii memory termination ? sstl-2 and sstl-3 termination ? hstl termination ? pc motherboards ? graphics boards ? disk drives ? cd-rom drives ? sourcing or sinking 2.5a for ddr-i ? sourcing or sinking 1.5a for ddr-ii ? av cc undervoltage lockout ? reference output ? minimum number of external components ? accurate internal voltage divider ? disable function, puts device into sleep mode ? thermal shutdown ? over current protection ? available in soic8-edp package ? pb-free, halogen free, and rohs/weee compliant description features applications sc2596 gnd en vsense vref vddq avcc pvcc vtt vref 0 en vtt avcc vddq
2 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management r e t e m a r a pr e t e m a r a p r e t e m a r a p r e t e m a r a pr e t e m a r a pl o b m y sl o b m y s l o b m y s l o b m y sl o b m y ss n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u e g a t l o v e c n e r e f e rv f e r i t u o _ f e r a m 0 =q d d v 9 4 . 0q d d v 5 . 0q d d v 1 5 . 0v v f e r e c n a d e p m i t u p t u oz f e r v i f e r a u 0 3 + o t a u 0 3 - =0 3 2 n o i t a l u g e r t u p t u o t t v ) 1 ( v ( t t v - f e r ) i t u o a 0 = i t u o a 5 . 1 - = i t u o a 5 . 1 + = 5 2 -05 2 +v m t n e r r u c t n e c s e i u qi q i d a o l a 0 =0 0 40 0 7a u v a c c d l o h s e r h t e l b a n e 1 . 22 . 2v e c n a d e p m i t u p n i q d d vz q d d v 0 0 1k n w o d t u h s n i t n e r r u c t n e c s e i u qi d s 0 = n e0 5 10 5 2a u t n e r r u c e g a k a e l n i p n ei d s _ q 0 = n e1a u e g a t l o v d l o h s e r h t n eh v l v 2 8 . 0 v n i t n e r r u c e g a k a e l t t v n w o d t u h s i l _ t t v , v 5 2 . 1 = t t v , v 0 = d s 5 2 t a o c 6a u r e t e m a r a pr e t e m a r a p r e t e m a r a p r e t e m a r a pr e t e m a r a p l o b m y sl o b m y s l o b m y s l o b m y sl o b m y sm u m i x a mm u m i x a m m u m i x a m m u m i x a mm u m i x a ms t i n us t i n u s t i n u s t i n us t i n u d n g o t n e , q d d v , c c v a , c c v p 0 . 6 + o t 3 . 0 -v e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h t c j 5 . 5 o w / c t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h t a j 5 . 6 3 o w / c e g n a r e r u t a r e p m e t n o i t c n u j m u m i x a mt j 5 2 1 + o t 0 4 - o c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 - o c s 0 4 - 0 1 e r u t a r e p m e t w o l f e r r i k a e pt g k p 0 6 2 o c ) l e d o m y d o b n a m u h ( g n i t a r d s ed s e2v k unless otherwise specified: t j = -40 o c to +125 o c, av cc = pv cc = 2.5v, v ddq = 2.5v. electrical characteristics (ddr-i) absolute maximum ratings exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2009 semtech corp. www.semtech.com power management sc2596 note: (1) regulation is measured by using a load current pulse. (pulse width less than 10ms, duty cycle less than 2%, t a = 25 o c) r e t e m a r a pr e t e m a r a p r e t e m a r a p r e t e m a r a pr e t e m a r a pl o b m y sl o b m y s l o b m y s l o b m y sl o b m y ss n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u t n e r r u c e s n e s v i e s n e s 0 50 0 2a n n w o d t u h s l a m r e h tt d s 0 6 1 o c s i s e r e t s y h n w o d t u h s l a m r e h tt s y h _ d s 0 1 o c electrical characteristics (ddr-i cont.) unless otherwise specified: t j = -40 o c to +125 o c, av cc = pv cc = 2.5v, v ddq = 2.5v. r e t e m a r a pr e t e m a r a p r e t e m a r a p r e t e m a r a pr e t e m a r a pl o b m y sl o b m y s l o b m y s l o b m y sl o b m y ss n o i t i d n o c t s e ts n o i t i d n o c t s e t s n o i t i d n o c t s e t s n o i t i d n o c t s e ts n o i t i d n o c t s e tn i mn i m n i m n i mn i mp y tp y t p y t p y tp y tx a mx a m x a m x a mx a ms t i n us t i n u s t i n u s t i n us t i n u e g a t l o v e c n e r e f e rv f e r i t u o _ f e r a m 0 =q d d v 9 4 . 0q d d v 5 . 0q d d v 1 5 . 0v v f e r e c n a d e p m i t u p t u oz f e r v i f e r a u 0 3 + o t a u 0 3 - =0 3 2 n o i t a l u g e r t u p t u o t t v ) 1 ( v ( t t v - f e r ) i t u o a 0 = i t u o a 0 . 1 - = i t u o a 0 . 1 + = 5 2 -05 2 +v m t n e r r u c t n e c s e i u qi q i d a o l a 0 =0 0 40 0 7a u v a c c d l o h s e r h t e l b a n e 1 . 22 . 2v e c n a d e p m i t u p n i q d d vz q d d v 0 0 1k n w o d t u h s n i t n e r r u c t n e c s e i u qi d s 0 = n e0 5 10 5 2a u t n e r r u c e g a k a e l n i p n ei d s _ q 0 = n e5 . 0a u e g a t l o v d l o h s e r h t n eh v l v 2 8 . 0 v n i t n e r r u c e g a k a e l t t v n w o d t u h s i l _ t t v , v 9 . 0 = t t v , v 0 = d s 5 2 t a o c 6a u t n e r r u c e s n e s v i e s n e s 0 50 0 2a n n w o d t u h s l a m r e h tt d s 0 6 1 o c s i s e r e t s y h n w o d t u h s l a m r e h tt s y h _ d s 0 1 o c unless otherwise specified: t j = -40 o c to +125 o c, av cc = 3.3v, pv cc = v ddq = 1.8v. electrical characteristics (ddr-ii) note: (1) regulation is measured by using a load current pulse. (pulse width less than 10ms, duty cycle less than 2%, t a = 25 o c)
4 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management waveforms start up. shut down. shut down by en. transient with +/- 1a load start up by en. 1a load avcc pvcc vtt io avcc pvcc vtt io avcc pvcc//vddq vtt io avcc pvcc//vddq vtt io avcc vddq//pvcc vref vtt avcc vddq//pvcc vref vtt avcc vddq//pvcc vref vtt avcc vddq//pvcc vref vtt avcc pvcc en vtt avcc pvcc en vtt avcc pvcc en vtt avcc pvcc en vtt
5 ? 2009 semtech corp. www.semtech.com power management sc2596 waveforms maximum sourcing current vs avcc. (vddq=1.8v, pvcc=2.5v) maximum sinking current vs avcc. (vddq=1.8v, pvcc=2.5v) maximum sinking current vs avcc. (vddq=1.8v, pvcc=1.8v) maximum sourcing current vs avcc. (vddq=1.8v, pvcc=1.8v) 2.0 2.5 3.0 3.5 4.0 22.533.544.555.5 avcc ( v) output current (a) 2.0 2.5 3.0 3.5 4.0 22.533.544.555.5 avcc ( v) output current (a) 1.0 1.5 2.0 2.5 3.0 22.533.544.555.5 avcc ( v) output current (a) 2.0 2.5 3.0 3.5 4.0 22.533.544.555.5 avcc ( v) output current (a)
6 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management pin configuration ordering information part number package (3) temp. range (t a ) sc2596setrt (1) soic8-edp -40 to +105 o c sc2596evb (2) evaluation board notes: (1) only available in tape and reel packaging. a reel contains 2500 devices for soic8-edp. (2) evb provided with soic8-edp package. (3) pb-free, halogen free, and rohs/weee compliant. 1 2 3 4 vtt gnd 5 6 7 8 pvcc en avcc vsense vddq vref top view (soic8-edp)
7 ? 2009 semtech corp. www.semtech.com power management sc2596 # n i p# n i p # n i p # n i p# n i pe m a n n i pe m a n n i p e m a n n i p e m a n n i pe m a n n i pn o i t c n u f n i pn o i t c n u f n i p n o i t c n u f n i p n o i t c n u f n i pn o i t c n u f n i p 1d n g. d n u o r g 2n e. w o l s i n i p n e n e h w d e l b a s i d s i 6 9 5 2 c s . n i p e l b a n e 3e s n e s v r o t i c a p a c c i m a r e c f n 0 0 1 o t f n 0 1 a t c e n n o c . n i p k c a b d e e f a s i n i p e s n e s v s i n i p e s n e s v o t e s o l c r o t i c a p a c s i h t e c a l p d n a d n u o r g o t n i p s i h t n e e w t e b . n o i t i d n o c t n e i s n a r t g n i r u d n o i t a l l i c s o d i o v a o t d e r i u q e r 4f e r v l a n r e t n i e h t f o t u p t u o d e r e f f u b e h t s e d i v o r p h c i h w , n i p t u p t u o n a s i n i p f e r v m o r f d e t c e n n o c e b d l u o h s r o t i c a p a c c i m a r e c f n 0 0 1 a . e g a t l o v e c n e r e f e r . e c a r t t r o h s h t i w d n u o r g o t n i p f e r v 5q d d v o t e g a t l o v e c n e r e f e r l a n r e t n i g n i t a e r c r o f n i p t u p n i n a s i n i p q d d v e h t . r e d i v i d r o t s i s e r l a n r e t n i n a o t d e t c e n n o c s i e g a t l o v q d d v e h t . t t v e t a l u g e r l a n r e t n i e h t o t d e t c e n n o c s i ) 2 / q d d v ( r e d i v i d r o t s i s e r f o p a t l a r t n e c e h t g n i t r e v n i - n o n e h t d n a n i p f e r v o t d e t c e n n o c s i t u p t u o h c i h w , r e f f u b e g a t l o v p o o l k c a b d e e f e h t h t i w . e g a t l o v e c n e r e f e r e h t s a r e i f i l p m a r o r r e e h t f o t u p n i s i t i . y l e s i c e r p 2 / q d d v e h t k c a r t s y a w l a l l i w e g a t l o v t u p t u o t t v e h t , d e s o l c e h t o t t x e n d e d d a e b d l u o h s r o t i c a p a c c i m a r e c f u 1 a t a h t d e d n e m m o c e r . y t i n u m m i e s i o n e h t e s a e r c n i o t d n u o r g o t n i p q d d v 6c c v a c c v a e h t . y r t i u c r i c l o r t n o c l a n r e t n i e h t f o l l a y l p p u s o t d e s u s i n i p c c v a e h t o t ) l a c i p y t v 1 . 2 ( e g a t l o v d l o h s e r h t o l v u s t i n a h t r e t a e r g e b o t s a h e g a t l o v n a h t r e w o l s i e g a t l o v c c v a f i . n o i t a r e p o l a m r o n n i e b o t 6 9 5 2 c s e h t w o l l a e c n a d e p m i h g i h n i e b d l u o h s n i p t t v e h t , e g a t l o v d l o h s e r h t o l v u e h t . s u t a t s 7c c v p d a o l s w a r d n i p t t v e h t e r e h w m o r f e g a t l o v l i a r e h t s e d i v o r p n i p c c v p e h t t s u m e g a t l o v c c v p e h t . c c v p d n a c c v a n e e w t e b n o i t a t i m i l a s i e r e h t . t n e r r u c . n o i t a l u g e r e g a t l o v t u p t u o t c e r r o c e h t e r u s n e o t e g a t l o v c c v a o t l a u q e r o s s e l e b e h t r e h g i h . e g a t l o v c c v p n o t n e d n e p e d s i y t i l i b a p a c t n e r r u c e c r u o s t t v e h t . t n e r r u c e c r u o s e h t r e h g i h , c c v p n o e g a t l o v 8t t v t n e r r u c s u o u n i t n o c e c r u o s d n a k n i s n a c t i . 6 9 5 2 c s f o t u p t u o e h t s i n i p t t v e h t d l u o h s e n o t a h t d e d n e m m o c e r s i t i . n o i t a l u g e r d a o l t n e l l e c x e g n i p e e k e l i h w r o r o t i c a p a c c i m a r e c f u 1 a d n a r o t i c a p a c r s e w o l f u 0 2 2 e n o t s a e l t a e s u , r o t i c a p a c c i m a r e c f u 8 . 6 a d n a r o t i c a p a c c i t y l o r t c e l e r s e h g i h f u 0 2 2 e n o e g a t l o v e h t g n i c u d e r d n u o r g o t e n a l p p i r t s t t v e h t n o d e c a l p e r a h c i h w . n o i t i d n o c t n e i s n a r t d a o l r e d n u e k i p s l a m r e h t d a p . s a i v e l p i t l u m g n i s u e n a l p d n u o r g o t t c e n n o c . s e s o p r u p g n i k n i s t a e h r o f d a p . y l l a n r e t n i d e t c e n n o c t o n pin descriptions
8 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management block diagram + - error amp. avcc gnd uvlo + thermal shutdown vddq vsense vtt anti- shoot- thru + driver circuit pvcc en vref + - vref buffer description description description description description sc2596 is a low-voltage, low-dropout ddr termination regulator with separate power supply to support both ddr1 and ddr2 applications. avcc and pvcc can be tied together for ddr1 and can also be separated for ddr2. sc2596 regulates vtt to the voltage of vref. vtt will sink or source upto 2.5a. internal shoot-through protec- tion ensure both top and bottom mosfet will not con- duct while maintaining fast source-to-sink load transient. thermal shut-down and internal current limit protect sc2596 from shorted load or over-heated vref buff vref buff vref buff vref buff vref buff vref is derived from vddq with an accurate divide by op-amps(vref buffer). it is capable to sink and source 30ua. it is used as the reference voltage to the error amp. a 100nf or higher capacitor is recommended for vref pin to ground; to enhance the noise immunity from board, an additional pull-down resistor (1m ) is recomanded as well from vref pin to ground. error amp error amp error amp error amp error amp low input offset op-amp for the main linear regulator. it controls the vtt output voltage and which side of the mosfet to turn on (or turn off) to achieve zero shoot through current. anti-shoot thought driver anti-shoot thought driver anti-shoot thought driver anti-shoot thought driver anti-shoot thought driver buffer stage takes the error voltage to control mosfet. internal current limit is incorporated to protect from shorted load. thermal shutdown & uvlo thermal shutdown & uvlo thermal shutdown & uvlo thermal shutdown & uvlo thermal shutdown & uvlo the thermal shutdown block prevent the junction tem- perature exceed 165 o c. uvlo circuit to ensure proper power is available for correct operation of the ic.
9 ? 2009 semtech corp. www.semtech.com power management sc2596 overview double data rate (ddr) sdram was defined by jedec 1997. its clock speed is the same as previous sdram but data transfer speed is twice than previous sdram. by now, the requirement voltage range is changed from 3.3v to 2.5v or 1.8v; the power dissipation is smaller than sdram. for above reasons, it is very popular and widely used in m/b, n/b, video-cards, cd rom drives, disk drives. regarding the ddr power management solution, there are two topologies can be selected for system design- ers. one is switching mode regulator that has bigger sink/ source current capability, but the cost is higher and needs more board space. another solution is linear mode regu- lator, which costs less, and needs less board space. for two dimm motherboards, system designers usually choose the linear mode regulator for ddr power man- agement solution. application information thermal shutdown the sc2596 has built-in thermal detected circuit to pre- vent this device from over temperature and damage. the sc2596 goes into shunt down mode when tem- perature is higher than 165 o c. the protection condition will release when the temperature of device drop down by 10 o c. avcc and pvcc avcc and pvcc are the input supply pins for the sc2596. avcc is supply voltage for all the internal control circuitry. the avcc voltage has to be greater than its uvlo thresh- old voltage (2.1v typical) to allow the sc2596 to be nor- mal operation. the pvcc pin provides the rail voltage from where the vtt pin draws load current. there is a limitation between avcc and pvcc. the pvcc voltage must be less or equal to avcc voltage to ensure the correct vtt output voltage regulation. vsense vsense pin is a feedback pin from vtt plane. vtt plane is always a narrow and long strip plane in most montherboard applications. this long strip plane will cause a large trace inductance and trace resistance. consider the load transient condition, a fast load cur- rent going through vtt strip plane will create a voltage spike on vtt plane and a dc voltage drop for load cur- rent. it is recommanded the vsense pin should be con- nected center of vtt plane to improve regulation and transient response. a longer trace of vsense may pick up noise and cause the error of load regulation. hence designer should avoid a longer trace between vsense to vtt plane. a 100nf ceramic capacitor close to vsense pin is required. vref vref pin is an output pin to provid internal reference voltage. system designer can use the voltage for northbridge chipset and memory. it is necessary to add a ceramic capacitor (100nf) from vref pin to ground with shortest trace. typical application circuits & waveforms four different application circuits are shown below in fig- ure 1, figure 2, figure 3 and figure 4. each circuit is designed for a specific condition. see note a. and b. below for recommended power up sequencing. application_1: standard sstl-2 application the avcc pin, pvcc pin and the v ddq pin can be tied together for sstl-2 application (figure 1). it only needs a 2.5v power rail for normal operation. system designer can save the pcb space and reduce the cost. figure 1: standard sstl-2 application. vref/1.25v 0 vddq/en=2.5v vtt/1.25v sc2596 sc2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 cin1 1uf cin1 1uf csense 100nf csense 100nf cin2 100uf cin2 100uf cout 220uf cout 220uf cref 100nf cref 100nf
10 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management application information (cont.) application_2: lower power loss configuration for sstl-2 if power loss is a major concern, separating the pvcc form avcc and vddq will be a good choice (figure 2). the pvcc can operate at lower voltage (1.8v to 2.5v) if 2.5v voltage is applied on avcc and the vddq, the source current is lower due to the lower operating voltage ap- plied on the pvcc. figure 2: lower power loss for sstl-2(ddr-i). application_4: high source current configuration if there is a need for vtt to source more current, espe- cially for ddr-ii applications, the system designer can tie the avcc and pvcc to 3.3v while has the vddq tie to 1.8v. this configuration can ensure more than 2a source and sink capability from the vtt rail. notes: (a) the preferred configuration for ddr-i applications is to tie avcc and pvcc to vddq, which is typically 2.5v. (b) if avcc and pvcc rails are tied together, then the vddq cannot lead the avcc and pvcc. figure 3: lower power loss for sstl-18(ddr-ii). vref/0.9v 0 avcc/pvcc=3.3v vddq=1.8v vtt/0.9v en cin2 100uf cin2 100uf cout 220uf cout 220uf cin1 1uf cin1 1uf cref 100nf cref 100nf 1m 1m csense 100nf csense 100nf cout 10uf cout 10uf sc2596 sc2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 vref/1.25v 0 pvcc=2.5v vddq/avcc=2.5v vtt/1.25v en/2.5v cin2 100uf cin2 100uf sc2596 sc2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 cin1 1uf cin1 1uf 1m 1m csense 100nf csense 100nf cout 220uf cout 220uf cref 100nf cref 100nf application_3: low power loss configuration for sstl-18(ddr-ii) if power loss is a major concern, setting the pvcc to be 2.5v will be a good choice (figure 3). the pvcc can op- erate at lower voltage. if 2.5v voltage is applied on avcc and pvcc, the source current is lower due to the lower operating voltage applied on the pvcc. vref/0.9v 0 avcc/pvcc=2.5v vddq=1.8v vtt/0.9v en cref 100nf cref 100nf cout 220uf cout 220uf cin2 100uf cin2 100uf sc2596 sc2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 csense 100nf csense 100nf 1m 1m cin1 1uf cin1 1uf figure 4: high current set up for sstl-18(ddr-ii). application_5: all ceramic capacitor configuration figure 5: all ceramic capacitor configuration. for some pure ceramic output capacitor designs, one needs to add small esr in series with the output capaci- tor in order to enhance stability margin. for example, an 100mohm external esr is suggested to help improve the phase margin for the circuit in figure 5. figure 6 shows the corresponding bode plot. en vtt/0.9v vref/0.9v 0 avcc=3.3v vddq/pvcc=1.8v external r 100mohm external r 100mohm csense 100nf csense 100nf sc2596 sc2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 1m 1m cout 10uf cout 10uf cref 100nf cref 100nf cin3 10uf cin3 10uf cin2 1uf cin2 1uf cin1 1uf cin1 1uf
11 ? 2009 semtech corp. www.semtech.com power management sc2596 layout guidelines 1) the soic8-edp package of sc2596 can improve the thermal impedance ( jc ) significantly. a suitable thermal pad should be add when pcb layout. some thermal vias are required to connect the thermal pad to the pcb ground layer. this will improve the thermal performance. please refer to the recommanded landing pattern. 2) to increase the noise immunity, a ceramic capacitor of 100nf is required to decouple the v ref pin with the shortest connection trace. 3) to reduce the noise on input power rail for standard sstl-2 application, a 100 f low esr capacitor and a 1 f ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection. 4) vtt output copper plane should be as large as possible. a 4.7uf to 10 f capacitor have to be used to decouple the vtt pin. 5) the trace between vsense pin and vtt rail should be as short as possible and put a 10nf ~100nf capacitor close this vsense pin. application information (cont.) io=380ma_soure 0.00 10.00 20.00 30.00 40.00 50.00 60.00 70.00 80.00 90.00 10mr 50mr 100mr 200mohm phase magnitude cout=4.7uf cout=10uf cout=22uf io=380ma_sink -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 100.00 120.00 10mr 50mr 100mr 200mohm phase magnitude cout=4.7uf cout=10uf cout=22uf figure 6: bode plot of an all ceramic capacitor application phase margin vs external esr application_5: bode plot of an all ceramic capacitor solution in figure 5. figure 7: phase margin vs external esr values for different output ceramic capacitor values the phase margin is 72 and the bandwidth is around 1mhz, where: avcc=3.3v, pvcc=vddq=1.8v, vtt=0.9v, iout=380ma, cout=10uf & 100mhom. for this application, we further measured the corresponding phase margins for different output capacitor values and esr values at designed sourcing and sinking currents in figure 7.
12 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management typical application circuit ddr-ii vtt solution bill of material f e rf e r f e r f e rf e ry t qy t q y t q y t qy t qe c n e r e f e re c n e r e f e r e c n e r e f e r e c n e r e f e re c n e r e f e re u l a v / r e b m u n t r a pe u l a v / r e b m u n t r a p e u l a v / r e b m u n t r a p e u l a v / r e b m u n t r a pe u l a v / r e b m u n t r a pr e r u t c a f u n a mr e r u t c a f u n a m r e r u t c a f u n a m r e r u t c a f u n a mr e r u t c a f u n a m 111 c3 0 6 0 , c i m a r e c , r 5 x , v 5 2 , f n 0 0 1o e g a y 212 c3 0 6 0 , c i m a r e c , r 5 x , v 6 1 , f n 0 1o e g a y 313 c3 0 6 0 , c i m a r e c , r 5 x , v 6 1 , f u 1o e g a y 416 c3 0 6 0 , c i m a r e c , r 5 x , v 6 1 , f u 1o e g a y 517 c3 0 6 0 , c i m a r e c , r 5 x , v 6 1 , f u 1o e g a y 614 cm u n i m u l a , v 3 . 6 , f u 0 0 1o e g a y 715 cm u n i m u l a , v 3 . 6 , f u 0 2 2n o c y b u r 811 rm h o m 1o e g a y 911 u6 9 5 2 c sh c e t m e s r1 1m c6 1uf c7 1uf c1 100nf u1 sc2596 gnd 1 en 2 vsense 3 vref 4 vddq 5 avcc 6 pvcc 7 vtt 8 vref 0 en c5 220uf vtt c4 100uf c3 1uf 0.9v vddq 3.3v 1.8v c2 10nf 0.9v
13 ? 2009 semtech corp. www.semtech.com power management sc2596 outline drawing - soic8-edp
14 ? 2009 semtech corp. www.semtech.com sc2596 preliminary power management land pattern - soic8-edp contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804

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